1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device in which a semiconductor substrate (wafer) having a plurality of semiconductor chips formed on one of principal surfaces of the substrate is cut into the semiconductor chips through dicing.
2. Description of the Related Art
In electronic devices, such as a sensor chip, in which the plurality of semiconductor devices are adjoined to each other and mounted as the module, it is necessary to shorten the distance between the adjacent semiconductor devices as much as possible, and make the sensor region continuous without interruption. What is required for such electronic devices is the technology which cuts the semiconductor wafer into semiconductor chips with high accuracy of the outside dimensions thereof.
To cut the semiconductor substrate (wafer) having the plurality of semiconductor chips formed on one of the principal surfaces of the substrate into the semiconductor chips, the dicing process which is known as one of cutting processes is performed. In this respect, the principal surfaces are usually the front and back surfaces of the substrate, and the semiconductor chips are formed on either the front surface or the back surface of the substrate.
In the dicing process, the wafer is cut into the chips while the cutting blade with the diamond particles embedded is rotated at high speed. Since the wafer is mechanically cut with the cutting blade and a region of the wafer corresponding to the blade width is lost, it is necessary to provide the wafer with the region which is needed for the cutting in the dicing process.
Generally, the width dimension of this region in the semiconductor wafer is determined by taking into consideration the blade width, the cutting accuracy, and the damage to the semiconductor chip.
Moreover, the dicing is classified into the two methods: the half cut method and the full cut method, depending on the quantity of cutting (depth) of the semiconductor substrate.
The half cut method is a method in which the semiconductor substrate is cut to a certain depth in the middle of the semiconductor substrate thickness. Usually, in the case of the half cut method, it is necessary to perform an additional cutting process (breaking) which cuts away the non-cut portion of the wafer after the end of the dicing process.
On the other hand, the full cut method is a method in which the semiconductor substrate is fully cut for the entire thickness of the semiconductor substrate. Consequently, the semiconductor substrate is cut to the depth at which the semiconductor chips are completely separated from each other.
In order to avoid scattering of the thus separated semiconductor chips, the full cut method requires performing, before the start of the dicing process, the process of attaching the dicing tape to fix the other of the principal surfaces of the substrate to the jig called the dicing frame.
Moreover, there are two kinds of methods: the single cut method and the double cut method, which are usually performed in the dicing process. In the case of the single cut method, a dicing groove is formed in the semiconductor substrate by performing a cutting action at a time. In the case of the double cut method, two dicing grooves are formed in the semiconductor substrate by performing a cutting action at a time.
For the purposes of reducing the influences of chipping around the cutting zone when performing the dicing process and reducing the influences caused by the decrease of the blade width due to the blade wear, the adoption of the double cut method attracts attention.
Concerning the dicing used for the semiconductor-device manufacturing method, there is known the conventional technology disclosed in Japanese Laid-Open Patent Applications No. 2003-045826, No. 10-083974 and No. 07-183255.
In the dicing technology of Japanese Laid-Open Patent Application No. 2003-045826, the semiconductor-device manufacturing method which uses the single cut method to form one dicing groove along with the dicing line is proposed.
However, in the above-mentioned single cut method, while the cutting process is advanced, the thickness of the dicing blade becomes thin, and variations of the dicing width in cutting the semiconductor substrate may be produced. This method is not appropriate for the case where high accuracy of the outside dimensions of the semiconductor chip is required. For example, the required accuracy of the outside dimensions is about +0/−15 micrometers to the target value.
In the dicing technology of Japanese Laid-Open Patent Applications No. 10-083974 and No. 07-183255, the method in which the cutting process is performed on both the front surface and the back surface of the semiconductor device is proposed.
However, in the above-mentioned method, the blade width becomes thin due to wearing of the blade produced every time the dicing action is performed at a time, and the accuracy of the outside dimensions becomes insufficient. Namely, the outside dimensions of the resulting semiconductor chip may be larger than the design values. This method is also inappropriate for the case where high accuracy of the outside dimensions of the semiconductor chip is required.
Accordingly, in the conventional dicing method using the single dicing blade, there is the problem in that the outside dimensions of the semiconductor chip vary depending on the change of the dicing blade width. To obviate the problem, the two-blade dicing method is proposed. In this method, two dicing blades are used, and the dicing is performed on the semiconductor substrate by placing the dicing blades in proximity to each other in the cutting zone.
FIG. 1 shows the structure of the dicing grooves in the semiconductor substrate which are formed according to the two-blade dicing method with the two dicing blades in proximity.
In FIG. 1, the reference numeral 1 denotes the semiconductor substrate (for example, silicon), 2 denotes the electrode layer which forms a part of the semiconductor chips formed on one of the principal surfaces (the front surface) of the semiconductor substrate 1, 4A and 4B denote the dicing grooves, and 6 denotes the inner side surface of each of the dicing grooves 4A and 4B. The dicing grooves 4A and 4B are located in proximity to the adjoining semiconductor chips and formed on both the sides of the dicing line between the adjoining semiconductor chips. The dicing grooves 4A and 4B are formed by cutting the semiconductor substrate 1 to the depth at which the other of the principal surfaces (the back surface) of the semiconductor substrate 1 is reached.
In the above-mentioned structure, the inner side surfaces (semiconductor chip side surface) 6 of the dicing grooves 4A and 4B are accurately cut at a fixed distance from the metal layer 2 at the outermost periphery of the semiconductor chip formation part. Thus, it is possible to obtain the outside dimensions of the semiconductor chip concerned at high accuracy.
However, the above-mentioned dicing process uses the full cut method in which the semiconductor substrate 1 is cut, on both the sides of the dicing line on the substrate 1, fully to the depth covering the entire thickness of the substrate 1.
For this reason, a crack may be produced on the back surface of the semiconductor substrate 1 at the back side portions 9 of the dicing grooves 4A and 4B. Moreover, the semiconductor substrate portion 7 located between the dicing groove 4A and the dicing groove 4B may disperse when the dicing is performed. This will become the cause of the damage of the semiconductor chip part.